Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis

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K. L. Shepard and D.-J. Kim, “Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis” Proceedings of the International Conference on Computer-Aided Design, 1999, pages 531-538

Return-limited inductances: A Practical Approach to On-Chip Inductance Extraction

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K. L. Shepard and Z. Tian, “Return-limited inductances: A Practical Approach to On-Chip Inductance Extraction” Proceedings of the 1999 Custom Integrated Circuits Conference.

Interconnect Parasitic Extraction in the Digital IC Design Methodology

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M. Kamon, S. McCormick, and K. L. Shepard, “Interconnect Parasitic Extraction in the Digital IC Design Methodology” Proceedings of the International Conference on Computer-Aided Design, 1999, pages 223-230.