Using full-rail interfaces on chip (in which CMOS inverters drive CMOS over RC-dominated interconnect) is a very energy inefficient means of communication (for a given amount of bandwidth density) and results in unnecessarily long wire latencies. We have been developing techniques to take full advantage of the transmission line properties of on-chip wires to achieve high-bandwidth, low-latency, and low-energy on-chip interconnects. One testchip, shown below, uses distributed shunt negative conductance elements to compensate for transmission line losses in a 14-mm long link.
A. P. Jose and K. L. Shepard, “Distributed loss-compensation techniques for energy-efficient low-latency on-chip communications” IEEE Journal of Solid-State Circuits, Vol. 42, June, 2007, pp. 1415-1424.
In this paper, we describe the use of distributed loss compensation to provide nearly transmission-line behavior for long on-chip interconnects. Negative impedance converters (NICs) inserted at regular intervals along an on-chip line are shown to reduce losses from more than 1 dB/mm to less than 0.3 dB/mm at 10 GHz. Results are presented for a 14-mm 3-Gb/s on-chip double-data-rate (DDR) link in 0.18- m CMOS technology, with a measured latency of 12.1 ps/mm and an energy consumption of less than 2 pJ/b with a BER 10 14. This constitutes a factor-of-three improvement in power and a one-and-a-half-times improvement in latency over an optimally repeated RC line of the same wire width.
A. P. Jose, G. Patounakis, and K. L. Shepard, “Pulse current-mode signalling for nearly speed-of-light intrachip communications” IEEE Journal of Solid-State Circuits, Vol. 41, April, 2006, pp. 772-780.
In this paper, we describe the design of on-chip repeater-less interconnects with nearly speed-of-light latency. Sharp current-pulse data transmission is used to modulate transmitter energy to higher frequencies, where the effect of wire inductance is maximized, allowing the on-chip wires to function as transmission lines with considerably reduced dispersion. A prototype 8-Gb/s serial link employing this pulsed current-mode signaling in a 0.18- m CMOS process is described and measured.
A. P. Jose and K. L. Shepard, “Distributed loss compensation for low-latency on-chip interconnects” Digest of Technical Papers, International Solid-State Circuits Conference, 2006.Continue reading →
A. P. Jose, G. Patounakis, and K. L. Shepard, “Near speed-of-light on-chip interconnects using pulsed current-mode signalling” Symposium on VLSI Circuits, 2005.Continue reading →