Circuits for intrachip communications and networks-on-chip
Using full-rail interfaces on chip (in which CMOS inverters drive CMOS over RC-dominated interconnect) is a very energy inefficient means of communication (for a given amount of bandwidth density) and results in unnecessarily long wire latencies. We have been developing techniques to take full advantage of the transmission line properties of on-chip wires to achieve high-bandwidth, low-latency, and low-energy on-chip interconnects. One testchip, shown below, uses distributed shunt negative conductance elements to compensate for transmission line losses in a 14-mm long link.
Related Publications
A. P. Jose and K. L. Shepard, “Distributed loss-compensation techniques for energy-efficient low-latency on-chip communications” IEEE Journal of Solid-State Circuits, Vol. 42, June, 2007, pp. 1415-1424.
Abstract
In this paper, we describe the use of distributed loss compensation to provide nearly transmission-line behavior for long on-chip interconnects. Negative impedance converters (NICs) inserted at regular intervals along an on-chip line are shown to reduce losses from more than 1 dB/mm to less than 0.3 dB/mm at 10 GHz. Results are presented for a 14-mm 3-Gb/s on-chip double-data-rate (DDR) link in 0.18- m CMOS technology, with a measured latency of 12.1 ps/mm and an energy consumption of less than 2 pJ/b with a BER 10 14. This constitutes a factor-of-three improvement in power and a one-and-a-half-times improvement in latency over an optimally repeated RC line of the same wire width.
A. P. Jose, G. Patounakis, and K. L. Shepard, “Pulse current-mode signalling for nearly speed-of-light intrachip communications” IEEE Journal of Solid-State Circuits, Vol. 41, April, 2006, pp. 772-780.
Abstract
In this paper, we describe the design of on-chip repeater-less interconnects with nearly speed-of-light latency. Sharp current-pulse data transmission is used to modulate transmitter energy to higher frequencies, where the effect of wire inductance is maximized, allowing the on-chip wires to function as transmission lines with considerably reduced dispersion. A prototype 8-Gb/s serial link employing this pulsed current-mode signaling in a 0.18- m CMOS process is described and measured.
A. P. Jose and K. L. Shepard, “Distributed loss compensation for low-latency on-chip interconnects” Digest of Technical Papers, International Solid-State Circuits Conference, 2006.
Continue reading →A. P. Jose, G. Patounakis, and K. L. Shepard, “Near speed-of-light on-chip interconnects using pulsed current-mode signalling” Symposium on VLSI Circuits, 2005.
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Process variability is a critical concern in nanometer-scale CMOS, owing to random device fluctuations (dopant fluctuation, line-edge roughness) and also reticle and proximity effects, which have difficult-to-predict impacts on device characteristics. Traditionally, process variability is characterized by one of two methods: either individual devices with pads are characterized on an automated wafer stepper or a ‘silicon dense’ structure of ring oscillators is used to find correlations between frequency and variation. The first method provides high accuracy at the cost of large area overhead and low information throughput. The second method, although providing higher throughput, ‘integrates’ all the characteristics of multiple devices into one measured number dramatically reducing information content
Recent methods focus on multiplexed transistor arrays because they provide high-density access to multiple devices for characterization. In our work, we have been designing on-chip current-voltage (I-V) measurement circuits that allow for rapid characterization of a large, dense array of multiplexed devices, using a four-point Kelvin-measurement approach to eliminate the effects of switch resistances and allowing for current measurements with nA resolution. Additionally, we have developed a novel, gate-leakage-insensitive on-chip charge-based capacitance measurement (CBCM) technique for capacitance-voltage (C-V)
Our on-chip I-V characterization approach is ideally suited for RTN characterization, as it allows relatively high-frequency (up to 100 KHz) current measurements with nA resolution on large statistical device sets. In our work, we have measured RTN noise in a low-power 45-nm process, and we have developed a characterization and statistical modeling methodology that allows us to capture the effects of RTN on transistor performance.
low-cost, portable, self-contained “gene chip” technology for nucleic acid measurement and detection. Much of this effort is focussed on developing active substrates based on fluorescence detection. One such active microarray is shown below, capable of time-resolved fluorescence detection for background rejection (though time-gating) and fluorescence-lifetime measurement. DNA probe is attached directly to the chip surface for detection.
Our most recent array design was capable of a maximum frame rate of 3.9 Hz and consisted of a 64 x 64 SPAD array with integrated timing and pixel control circuitry in 0.35μm technology. The image on this page below shows a FLIM image of quantum dots (in color) next to a CCD image showing the location of the quantum dots on the array.
A thin-film bulk acoustic resonator (FBAR) can be employed as the micron-scale equivalent of a quartz crystal microbalance (QCM); mass attaches to the surface of a piezoelectric crystal, causing the resonance frequency to decrease slightly. Whereas a quartz crystal sensor operates in the megahertz regime, FBAR structures resonate in the low gigahertz regime. Their small size allows array integration of sensors, similar to a microarray, and the increased frequency allows increased sensitivity. Both of these features make FBARs ideal for direct CMOS integration, where sensors can be built in dense arrays and used without bulky external measurement equipment.
In this research, we have fabricated FBAR structures monolithically on a custom CMOS substrate. The resonators are solidly mounted, and mechanical isolation is achieved with a multi-layer acoustic reflector. Monolithic fabrication enables an array of integrated resonators, and the underlying CMOS circuitry forms an independent FBAR-CMOS oscillator around each device. The CMOS substrate also contains a dedicated digital frequency counter for each oscillator, enabling parallel on-chip
On-chiposcillators at 850 MHz and 1.45 GHz have been demonstrated, and the integrated sensors have a mass sensitivity many times higher than that of a traditional QCM. In addition to sensing, this methodology may find significant utility in RF applications, where it enables monolithic integration of high-Q elements directly on a standard CMOS substrate.
