BIOEE | Random telegraph noise in 45-nm CMOS: analysis using an on-chip test and measurement system

S. Realov and K. L. Shepard, “Random telegraph noise in 45-nm CMOS: analysis using an on-chip test and measurement system,” International Electron Devices Meeting, 2010, pp. 28.2.1-28.2.4.

Abstract

RTN measurements in 45-nm CMOS across device bias and geometry using an on-chip characterization system are reported. An automated methodology for extracting RTN levels, amplitude and dwell times is developed. Complex RTN magnitude is statistically modeled, and device size and bias parameter dependencies of the developed model are examined.