Publications – 2025

Optical imaging offers a number of advantages over electrophysiology including cell-type specificity. However, its application has been limited to the investigation of shallow brain regions (less than 2 mm) because of the light scattering property of brain tissue. Passive optical conduits, such as graded-index lenses and waveguides, have permitted access to deeper locales but with restricted resolution and field of view, while creating massive lesions along the inserted path. Here we report an implantable complementary metal–oxide–semiconductor fluorescence imager with single-neuron resolution. The imager has a 512-pixel silicon image sensor post-processed into a 4.1-mm-long, 120-μm-wide shank with a collinear fibre for illumination. It can record transient fluorescent signals in deep brain regions at 400 frames per second. We show that the system can offer single-neuron resolution in functional imaging of GCaMP6s-expressing neurons at a frame rate of 400 frames per second.

Brain-computer interface (BCI) technology is among the fastest growing fields in research and development. On the application side, BCIs provide a deeper understanding of brain function, inspire the creation of complex computational models, and hold significant promise for assisting individuals with disabilities. On the system side, BCIs have evolved from non-invasive, low-resolution wearable devices to invasive, high-resolution, implantable systems-on-chip (SoCs) that offer higher-quality brain data, enabling more effective exploration of brain activity. However, implantable BCIs must acquire large-scale neural signals and run real-time BCI applications, all while relying on wireless communication for practical use. Unlike typical devices, BCIs must operate within strict power constraints to ensure safety, which is crucial for their deployment in real-world applications. This requires careful co-design and a balanced approach across the key components of the BCI system.
In this work, we discuss why BCIs present unique design challenges compared to conventional computing systems. We develop equations based on the system-level structure of modern BCIs to estimate power consumption and explore trade-offs among key system components: data acquisition, on-chip computation, and wireless communication. Using these equations, we analyze BCI SoC designs that support wireless communication and examine how scaling trends, design constraints, and optimization strategies may impact the feasibility of future BCIs. Specifically, we show a clear discrepancy between certain cutting-edge, BCI-centric computations and the feasibility of their on-chip integration in power-constrained BCI systems, revealing a significant gap between the development of deep learning methods for BCI and the design of safe BCI systems. However, with targeted optimizations in BCI system design and greater specialization for specific applications, future BCI systems will be able to successfully integrate modern BCI applications and advance toward widespread adoption.

We present EPOCHS-1, a 12 nm, 64 mm2 system-on-chip (SoC) with a high degree of heterogeneity. It features four Linux-SMP-capable RISC-V cores, 14 different types of accelerators, a distributed memory hierarchy, and various peripherals. EPOCHS-1’s memory hierarchy has the flexibility to support a diverse set of accelerators and can scale to support complex applications with 34% and 25% reduction in latency and energy, respectively. A subset of the SoC’s 23 power and 35 clock domains is regulated with a fully-decentralized power-allocation scheme and hybrid unified voltage and frequency scaling (HUVFS) that combines an in-package switched regulator with a per-tile low dropout (LDO). Combined, these techniques achieve up to a 1.57× speedup versus a centralized power management baseline. Designed with an agile methodology, EPOCHS-1 is based on an open-source SoC architecture and features only open-source components, either third-party or newly designed, thus enabling design reuse for future research projects.

Recent studies have demonstrated that the mechanisms through which biopolymers like RNA interconvert between multiple folded structures are critical for their cellular functions. A major obstacle to elucidating these mechanisms is the lack of experimental approaches that can resolve these interconversions between functionally relevant biomolecular structures. Here, we dissect the complete set of structural rearrangements executed by an ultra-stable RNA, the UUCG stem-loop, at the single-molecule level using a nano-electronic device with microsecond time resolution. We show that the stem-loop samples at least four conformations along two folding pathways leading to two distinct folded structures, only one of which has been previously observed. By modulating its flexibility, the stem-loop can adaptively select between these pathways, enabling it to both fold rapidly and resist unfolding. This mechanism of stabilization through compensatory changes in flexibility broadens our understanding of stable RNA structures and we expect it to serve as a general strategy that can be employed by all biopolymers.

The increase in both the number and the types of accelerators in modern systems on chip (SoCs) necessitates a rethinking of power management (PM) strategies. To overcome the scalability shortcomings of current methods, we propose BlitzCoin, a fully decentralized hardware-based PM coupled with optimized unified voltage and frequency regulation. We evaluated BlitzCoin through register transfer-level simulations of multiple SoCs targeted toward different application domains. The results are further validated through silicon measurements of a fabricated 12-nm many-accelerator SoC that includes BlitzCoin. Our evaluations show that BlitzCoin is markedly faster than state-of-the-art centralized PM strategies, with 8 × to 12 × lower response times. This results in 25%–34% throughput improvement and allows for scaling to 7 × to 13 × larger SoCs, all with a small area overhead of <1%. BlitzCoin is an addition to the open source ESP SoC platform, offering a foundation for further exploration of PM strategies.