Publications – 2006

Yield and variability are becoming detractors for successful design in sub-90 nm process technologies. We consider the fundamental lithography and process issues that are driving variability and yield and the role of design rules in future processes. We
examine the importance of layout-aware modeling and layout regularity, including advantages and cost. Characterization structures for examining the electrical effects of device-level variability are discussed as well as circuit techniques for mitigating variability and yield challenges.

Surface-based sensing assays based on fluorescence-based detection have become commonplace for both environmental and biomedical diagnostics. Traditional array scanners are expensive, large, and complex instruments. This paper describes the design of an active CMOS biosensor substrate for fluorescence-based assays that enables time-gated, time-resolved fluorescence spectroscopy without the need for an external reader. The array is sensitive to photon densities as low as 1 15 108 cm2, has a dynamic range of over 74 dB, and has subnanosecond timing resolution. Sensitivity is achieved through subsampling and averaging.

In this paper, we describe the design and implementation of a continuous time finite-impulse-response processor chain, which includes a 6-bit asynchronous ADC, an asynchronous digital core, and an 8-bit asynchronous DAC designed in TSMC 0.25- m technology. The continuous-time, discrete-amplitude systems combine benefits associated with analog and digital systems. Discrete-amplitude representations leverage the noise immunity and robustness of digital implementations. Continuous-time, nonsampled operation prevents aliasing and reduces the in-band quantization noise associated with the aliasing of subharmonic components. We present measurement results demonstrating an audio low-pass filter with a bandwidth of 6.0 kH.

This paper presents a distributed differential oscillator global clock network where the clock capacitance is rendered resonant with a set of on-chip spiral inductors. The clock amplitude and clock phase are both uniform across the entire global distribution, making this design scalable and compatible with existing local clocking methodologies. The resonant network, combined with phase averaging of the distributed oscillator, provides high immunity to process-, voltage-, and temperature-variation induced timing uncertainty. Measurement results from a prototype design implemented in a 0.18- m CMOS technology show almost an order of magnitude less jitter and power than a traditional treedriven grid global clock distribution. On-chip measurement circuits are used to characterize the jitter on the test chip, while a simulation model is used to examine skew and higher-order resonances in the resonant clock network.

DNA monolayers are widely used in fundamental and applied genomics and are versatile experimental models for elucidating the behavior of charged polymers at interfaces. The physical behavior of these systems is to a large extent governed by their internal ionic microenvironment, which is investigated here for layers of end-tethered, single-stranded DNA oligonucleotides (DNA brushes). Retention of counterions by the DNA brush manifests as lowered susceptibility of the interfacial capacitance to external salt conditions. A physical model based on concepts adapted from polymer science was used to further elucidate the connection between monolayer organization and its charging behavior. The data indicate a reorganization of the monolayer with changes in ionic strength and strand coverage that is consistent with that expected for a polyelectrolyte brush. A method for electrochemical quantification of strand coverage, based on shift of reduction potential for redox counterions associated with the DNA monolayer, is also described. These results provide guidance for development of label free electrochemical diagnostics employing DNA monolayers and formulate a description of monolayer behavior within a polymer science framework.

In this paper, we describe a technique for delivering power to a digital integrated circuit at high voltages, reducing current demands and easing requirements on power-ground network impedances. The design approach consists of stacking CMOS logic domains to operate from a voltage supply that is a multiple of the nominal supply voltage. DC–DC downconversion is performed using charge recycling without the need for explicit downconverters. Experimental results are presented for the prototype system in a 0.18- m CMOS technology operating at both 3.6 V and 5.4 V. Peak energy efficiencies as high as 93% are demonstrated at 3.6 V.

In this paper, we describe the design of on-chip repeater-less interconnects with nearly speed-of-light latency. Sharp current-pulse data transmission is used to modulate transmitter energy to higher frequencies, where the effect of wire inductance is maximized, allowing the on-chip wires to function as transmission lines with considerably reduced dispersion. A prototype 8-Gb/s serial link employing this pulsed current-mode signaling in a 0.18- m CMOS process is described and measured.