Publications – 2007
Z. Xu and K. L. Shepard, “Low-jitter active deskewing through injection-locked resonant clocking” IEEE Custom Integrated Circuits Conference, 2007.
Active deskewing is an important technique for managing variability in clock distributions but introduces latency and power-supply-noise sensitivity to the resulting networks. In this paper, we demonstrate how active deskewing can be achieved with resonant distributions without introducing significant jitter. The prototype network operates at a nominal 2-GHz frequency in a 0.18μm CMOS technology with more than 25 pF/mm2 of clock loading.
I. Meric, V. Caruso, R. Caldwell, J. Hone, K. L. Shepard, and S. J. Wind, “Hybrid carbon nanotube-silicon CMOS circuit” Journal of Vacuum Science and Technology B, 25, 6 (Nov/Dec, 2007), pp. 2577-2580
A hybrid technology is presented that combines carbon nanotube field-effect transistors (CNFET) with conventional, silicon-based complementary metal oxide semiconductor (CMOS) technology. The fabrication involves the chemical vapor deposition growth and optical characterization of carbon nanotubes, which are then transferred with lithographic precision onto a commercially fabricated CMOS substrate. In this manner, CNFET devices are fabricated on top of the interconnection network of the CMOS chip, providing a three-dimensional integration of active devices, “sandwiching” wiring, and passives. As a demonstration of this approach, a simple hybrid CNFET/CMOS inverter is fabricated and tested.
T.-C. Huang, S. Sorgenfrei, K. L. Shepard, P. Gong, and R. Levicky, “A CMOS array sensor for sub-800-ps time-resolved fluorescence detection” IEEE Custom Integrated Circuits Conference, 2007.
This paper describes the design of an active CMOS sensor array for fluorescence applications which enables timegated, time-resolved fluorescence spectroscopy. The 64 x 64 array is sensitive to photon densities as low as 8 x 106 photons/ cm2 with 64-point averaging and, through a differential pixel design, has a measured impulse response of better than 800 ps. Applications include both active microarrays and high-frame-rate imagers for fluorescence lifetime imaging microscopy.
P. M. Levine, P. Gong, K. L. Shepard, and R. Levicky, “Active CMOS array for electrochemical sensing of biomolecules” IEEE Custom Integrated Circuits Conference, 2007.
We describe the design of a 4Å~4 active sensor array for multiplexed electrochemical biomolecular detection in a 0.25- μm-CMOS process. Integrated potentiostats sense the current flowing through the on-chip Au electrodes that result from reactions occurring at the chip surface. Preliminary experimental results include cyclic voltammetry of several redox species and application to DNA probe coverage characterization.
K. A. Jenkins, K. L. Shepard, and Zheng Xu, “On-chip circuit for measuring period jitter and skew of clock distribution networks” IEEE Custom Integrated Circuits Conference, 2007.
A circuit for on-chip measurement of period jitter and skew of clock distribution is described. The circuit uses a single latch and a voltage-controlled delay element. The circuit is evaluated in a stand-alone pad frame, where a jitter resolution of about 1 ps is demonstrated, and is incorporated in a 2 GHz clock distribution network to obtain on-chip period jitter and clock skew measurement.
V. Wang and K. L. Shepard, “On-chip transistor characterisation arrays for variability analysis” Electronics Letters, Vol. 43, No. 15, July, 19, 2007.
efficiently and accurately characterise large, dense arrays of transistors for variability studies is designed. The prototype macro is used to perform current–voltage characterisation of a 2.8 mm2, 1600- transistor array with digital interfaces.
D. E. Schwartz, E. Charbon, and K. L. Shepard, “A single-photon avalanche diode imager for fluorescence lifetime applications” Symposium on VLSI Circuits, 2007, pp. 144-245.
A 64-by-64-pixel CMOS single-photon avalanche diode (SPAD) imager for time-resolved fluorescence detection features actively quenched and reset pixels, allowing gated detection to eliminate pile-up nonlinearities common to most time-correlated single-photon counting (TCSPC) approaches. Reset Timing information is collected using an on-chip time-tocalb calibrated digital converter (TDC) based on a counter and a supply- interpolators regulated delay-locked loop (DLL).
A. P. Jose and K. L. Shepard, “Distributed loss-compensation techniques for energy-efficient low-latency on-chip communications” IEEE Journal of Solid-State Circuits, Vol. 42, June, 2007, pp. 1415-1424.
In this paper, we describe the use of distributed loss compensation to provide nearly transmission-line behavior for long on-chip interconnects. Negative impedance converters (NICs) inserted at regular intervals along an on-chip line are shown to reduce losses from more than 1 dB/mm to less than 0.3 dB/mm at 10 GHz. Results are presented for a 14-mm 3-Gb/s on-chip double-data-rate (DDR) link in 0.18- m CMOS technology, with a measured latency of 12.1 ps/mm and an energy consumption of less than 2 pJ/b with a BER 10 14. This constitutes a factor-of-three improvement in power and a one-and-a-half-times improvement in latency over an optimally repeated RC line of the same wire width.