Mantovani P, Cota EG, Tien K, Pilato C, Di Guglielmo G, Shepard K, Carloni LP. An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems. InProceedings of the 53rd Annual Design Automation Conference 2016 Jun 5 (pp. 1-6).
Emerging technologies provide SoCs with fine-grained DVFS capabilities both in space (number of domains) and time (transients in the order of tens of nanoseconds). Analyzing these systems requires cycle-accurate accounting of rapidly-changing dynamics and complex interactions among accelerators, interconnect, memory, and OS. We present an FPGA-based infrastructure that facilitates such analyses for high-performance embedded systems. We show how our infrastructure can be used to first generate SoCs with looselycoupled accelerators, and then perform design-space exploration considering several DVFS policies under full-system workload scenarios, sweeping spatial and temporal domain granularity.