B. Calhoun, Y. Cao, X. Li, K. Mai. L. Pileggi, R. A. Rutenbar, and K. L. Shepard, “Digital circuit design challenges and opportunities in the era of nanoscale CMOS” Proceedings of the IEEE, 96, 2 (February, 2008) pp. 343-365
Well-designed circuits are one key “insulating” layer between the increasingly unruly behavior of scaled complementary metal–oxide–semiconductor devices and the systems we seek to construct from them. As we move forward into the nanoscale regime, circuit design is burdened to “hide” more of the problems intrinsic to deeply scaled devices. How this is being accomplished is the subject of this paper. We discuss new techniques for logic circuits and interconnect, for memory, and for clock and power distribution. We survey work to build accurate simulation models for nanoscale devices. We discuss the unique problems posed by nanoscale lithography and the role of geometrically regular circuits as one promising solution. Finally, we look at recent computer-aided design efforts in modeling, analysis, and optimization for nanoscale designs with ever increasing amounts of statistical variation.