S. C. Chan, K. L. Shepard, and P. J. Restle, “Distributed differential oscillators for global clock networks” IEEE Journal of Solid-State Circuits, September, 2006, pp. 2083-2094.
This paper presents a distributed differential oscillator global clock network where the clock capacitance is rendered resonant with a set of on-chip spiral inductors. The clock amplitude and clock phase are both uniform across the entire global distribution, making this design scalable and compatible with existing local clocking methodologies. The resonant network, combined with phase averaging of the distributed oscillator, provides high immunity to process-, voltage-, and temperature-variation induced timing uncertainty. Measurement results from a prototype design implemented in a 0.18- m CMOS technology show almost an order of magnitude less jitter and power than a traditional treedriven grid global clock distribution. On-chip measurement circuits are used to characterize the jitter on the test chip, while a simulation model is used to examine skew and higher-order resonances in the resonant clock network.