S. Realov and K. L. Shepard, “On-Chip Combined C-V/I-V Characterization System in 45-nm CMOS Technology,” IEEE Journal of Solid-State Circuits, Vol. 48, No. 3, March 2013.
An on-chip system for combined capacitance-voltage (C-V) and current-voltage (I-V) characterization of a large integrated transistor array implemented in a 45-nm bulk CMOS process is presented. On-chip I-V characterization is implemented using a four-point Kelvin measurement technique with 12-bit sub-10 nA current measurement resolution, 10-bit sub-1 mV voltage measurement resolution, and sampling speeds on the order of 100 kHz. C-V characterization is performed using a novel leakage- and parasitics-insensitive charge-based capacitance measurement (CBCM) technique with atto-Farad resolution. The on-chip system is employed in studying both random and systematic sources of quasi-static device variability. For the first time, combined C-V/I-V characterization of circuit-representative devices is demonstrated and used to extract variations in the underlying physical characteristics of the device, including line-edge-roughness (LER) parameters and systematic device length variations across the die.