Yield and variability are becoming detractors for successful design in sub-90 nm process technologies. We consider the fundamental lithography and process issues that are driving variability and yield and the role of design rules in future processes. We
examine the importance of layout-aware modeling and layout regularity, including advantages and cost. Characterization structures for examining the electrical effects of device-level variability are discussed as well as circuit techniques for mitigating variability and yield challenges.